Walkthrough

Introduces host memory-awareness for UCP memory-type endpoints, implements a per-endpoint CUDA flush mechanism with stream event tracking, removes the enable_same_process configuration option from CUDA IPC, updates endpoint flush bindings across CUDA transports, and adjusts tests accordingly.

Changes

Sequence Diagram(s)

sequenceDiagram
    participant Caller
    participant EP as CUDA EP
    participant Flush as Flush Handler
    participant Streams as Active Streams
    participant Completion
    
    Caller->>EP: uct_cuda_base_ep_flush()
    alt No active streams
        EP-->>Caller: UCS_OK (immediate)
    else Active streams exist
        EP->>Flush: Allocate base flush descriptor
        loop For each active stream
            EP->>Streams: Allocate per-stream flush descriptor
            Streams->>Streams: Register callback on stream event queue
            EP->>EP: Increment shared stream_counter
        end
        EP-->>Caller: UCS_INPROGRESS
        par Stream Processing
            Streams->>Streams: Process stream events
            Streams->>Flush: Invoke completion callback when counter reaches zero
            Flush->>Completion: Call user completion
            Flush->>Flush: Free flush descriptor
        end
    end

Estimated code review effort

🎯 3 (Moderate) | ⏱️ ~20 minutes

• Attention areas:
  • CUDA flush mechanism logic in cuda_iface.c: verify event enqueuing, counter synchronization, and callback sequencing
  • Memory-type endpoint constraints in ucp_ep.c: confirm host memory access intersection logic and lane count assertions
  • Configuration removal impact: ensure enable_same_process removal doesn't break backward compatibility expectations
  • Test changes in test_uct_iface.cc: verify that removal of self_unreachable test class is intentional and doesn't mask regressions

Suggested reviewers

• ofirfarjun7

Poem

🐰 A flush flows swift through streams aligned,
Per-EP events now well-designed,
Same-process flags we leave behind,
With memory-types and lanes refined,
The CUDA path now intertwined! ✨

Pre-merge checks and finishing touches

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